This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-277108, filed Sep. 12, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention generally relates to a peripheral circuit of a DRAM. More particularly, it relates to a semiconductor memory device adapted to use a masking method that makes it capable of masking data to be written.
2. Description of the Related Art
Single data rate (SDR)-synchronous DRAMs (SDRAMs) are being popularly used at present. SDR-SDRAMs are capable of specifying various functional features for itself according to the objective of the user of using the device. For example, it is possible to mask a part of the data to be written so that the part may not be actually written. For that purpose, SDR-SDRAMs are provided with a pin for supplying mask data that is referred to as DM pin.
While the user may use the data mask in various different ways, it is often and primarily used to mask the last data to be written in order to avoid collisions of data on the internal data path at the time of an interrupt.
The data mask method (DM) and the variable write burst length (VW) method are two popular methods for masking data.
FIG. 13 is a timing chart for both the DM method and the VW method illustrated in terms of burst length.
For example, referring to FIG. 13, if control signal DMIN fed to the DM pin is set to level HIGH for the purpose of writing data D0 through D7 with a burst length of BL=8 in synchronism with clock signal CLK, data D4, D5, D6 and D7 that correspond to the level HIGH period are masked.
With the DM method, once a write operation is started, the next command cannot be input until the time period necessary for processing all the data for the selected burst length is over. Referring again to FIG. 13, if the last four data do no need to be written at BL=8, it is not possible with the DM method to enter the next command until a clock cycle for eight data is over. This means that clock cycles are wasted for nothing.
On the other hand, with the VW method, data are masked by selecting a burst length that is different from that of the mode register when entering a write command. More specifically, a higher order address VWadd showing the burst length is input by using an unused pin simultaneously at the time of inputting a write command. Then, a burst length WBLn is defined for writing data as a function of the higher order address VWadd. Only data for the defined burst length WBLn are written in the memory cell array, while all the other data are masked.
With the VW method, the write operation is terminated immediately before the masked data and then data are no longer supplied to the data path. Thus, no collisions of data occur on the data path and hence the next write command can be input without problem. Then, the path occupancy ratio can be improved. Additionally, unlike the DM method, it is not necessary to provide a dedicated DM pin and hence the VW method can do with a reduced number of pins.
Meanwhile, various fast cycle RAMs (FCRAMs) and double data rate-SDRAMs (DDRIIs) have been proposed recently. The next generation high speed DRAMs including FCRAMs and DDRIIs use chip scale packages (CSPs). One of the significant problems of CSPs in terms of assembling is to provide an enough space for arranging solder balls and also for internal wiring. The VW method can operate with a reduced number of pins if compared with the DM method. In other words, the VW method is advantageous to the DM method in terms of assembling. Therefore, the VW method is expected to be applied to FCRAMs and DDRIIs.
However, this kind of memory devices are now in the transitional period of moving from the DM method to the VW method. In other words, at present there are users who are using the DM method and those who are using the VW method. Therefore, there is a demand for semiconductor memory devices that can adapt themselves to both the DM method and the VW method by means of a single chip.
In an aspect of the invention, there is provided a semiconductor memory device comprising: a specifying circuit for specifying one of the first masking method and the second masking method; a first generation circuit for generating a signal corresponding to the first masking method; a second generation circuit for generating a signal corresponding to the second masking method; and a third generation circuit connected to the output terminal of the second generation circuit; wherein the third generation circuit configured to generate a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification made by the specifying circuit of the first masking method and on the basis of the output signal of the second generation circuit in response to the specification made by the specifying circuit of the second masking method.